`make`

Maintain, update, and regenerate groups of programs (POSIX)

Syntax:

make [options] [macro=name] [target]

Options:

-C directory: Change to the given directory before doing anything.
-d: Display debugging information.
-e: Cause environment variables to override macro assignments within makefiles.
-f makefile: Use the description file makefile. If the pathname is the dash character (-), standard input is used. The default file is makefile or Makefile.
If there are multiple instances of this option, they're processed in the order specified.
-h: Display help information.
-i: Ignore error codes returned by commands. This is equivalent to the special .IGNORE: target.
-I directory: Search directory for included makefiles.
-j [N]: Allow N jobs at once. The default is infinite.
-k: If an unignored error occurs while executing the commands to bring a target up-to-date, abandon work on the current target, but continue with targets that don't depend on the current target. This is the opposite of -S. If both -k and -S are specified, the last one specified is used.
-l [N]: Don't start multiple jobs unless the load is below N. If N isn't specified, this option removes a previous load limit.
-n: No-execution mode. Print commands, but don't execute them. However, lines preceded by a plus sign (+) prefix or containing the string $(make) are executed. Lines beginning with an @ are printed.
-o file: Consider file to be very old and don't remake it.
-p: Write to standard output the complete set of macro definitions and target descriptions.
-q: Question mode. The make utility returns a zero or nonzero status code, depending on whether or not the target file is up-to-date. Targets aren't updated if this option is specified.
-r: Clear the suffix list and don't use the default inference rules.
-s: Be silent. Don't print command lines before executing them. This is equivalent to the special .SILENT: target.
-S: Undo the effect of the -k option. Stop processing when a nonzero exit status is returned by a command. If both -k and -S are specified, the last one specified is used. This option overrides the presence of the k flag in the MAKEFLAGS environment variable.
-t: Touch the target files, changing only the file date, rather than perform the rules to reconstruct them.
-v: Print the version number of make, and then exit.
-w: Print the current directory.
-W file: Consider file to be infinitely new.
--no-print-directory: Turn off -w, even if it was turned on implicitly.
--warn-undefined-variables: Warn when an undefined variable is referenced.
target_name: The target to bring up-to-date. If no target is specified, make uses the first target defined in the first makefile encountered.
macro=name: Macro definition. This definition remains fixed for the make invocation. It overrides any regular definitions for the specified macro within the makefiles and from the environment. This definition is inherited by subordinate make sessions but acts as an environment variable for these. That is, depending on the -e setting, it may be overridden by a makefile definition.

The make utility is used to maintain current versions of files by resolving time dependencies. If the file that make is examining (i.e. the target) is older than the file(s) on which it depends (i.e. the prerequisites), then make executes a list of shell commands associated with the target to create or update the target.

To control what make does, the utility refers to specifications (rules) consisting of a target, prerequisites, and a list of shell commands to be executed when a prerequisite is newer than the target. To simplify maintenance of programs, make has a collection of default macros and inference rules allowing it to identify the proper procedures required to update targets based on minimal information. (If the -r option is given, the builtin rules aren't used.)

For example, to compile myprog.c and produce the executable program myprog:

make myprog

This works even in the absence of a makefile. The alternative of using the qcc utility produces an executable named a.out by default. Using make for compiling single-source executables is a convenient shortcut.

When cross compiling, you can't rely on the default rules; you need to specify the target.

The make utility attempts to perform the actions required to ensure that the specified target(s) are up-to-date. A target is considered out-of-date if it's older than any of its prerequisites. The make utility treats all prerequisites as targets themselves and recursively ensures that they're up-to-date. The utility examines the modified times of files to determine whether they're out-of-date.

After all the prerequisites of a target are ensured to be up-to-date, and if the target is out-of-date, the shell commands associated with the target entry are executed. If no shell commands are listed for the target, it's treated as up-to-date.

For more information on make and writing makefiles, see the GNU website at http://www.gnu.org/.

Examples:

make myfile.o

Typing this in the absence of a makefile (or with a makefile that doesn't mention the myfile.o file) uses the builtin suffixes list and inference rules to determine the name of the source file and, if necessary, to run the proper command to create or rebuild the myfile.o file.

Suppose you have the source files myfile1.c, myfile2.c, and myfile3.c. The first two files include the headers <hdr1.h> and <hdr2.h>, and these files are all linked together to produce the program myprog. Here's what a simple makefile describing this could look like:

#  Samplemakefile1

myprog:  myfile1.o myfile2.o myfile3.o

myfile1.o:  hdr1.h hdr2.h

myfile2.o:  hdr1.h hdr2.h

myfile3.o:

To compile and link myprog:

make myprog

Or since myprog is the first target:

make

To see what commands need to be executed without actually executing them:

make -n

Using macros, the myprog makefile could be simplified to:

#  Samplemakefile2

OBJS=myfile1.o myfile2.o myfile3.o
HDRS=hdr1.h hdr2.h

myprog:  $(OBJS)

myfile1.o:  $(HDRS)

myfile2.o:  $(HDRS)

This makefile is functionally identical to the previous example. It isn't significantly better, just slightly more generalized.

We can further simplify the makefile by using the builtin inference rules and macros, as follows:

#  Samplemakefile3

OBJS=myfile1.o myfile2.o myfile3.o
HDRS=hdr1.h hdr2.h

myprog:  $(OBJS)

myfile1.o myfile2.o: $(HDRS)

As you can see, this makefile is short and to-the-point. Again, this is functionally equivalent to the previous examples.

Using this makefile, you can customize the compilation from the make command line by setting the appropriate macros:

make CFLAGS="-DHITHERE"

which defines the symbol HITHERE.

You can also direct the linker to produce a linkmap:

make LDFLAGS=-M

Of course, any of these macro assignments could be “hard-coded” in the makefile, but it's often convenient to override the defaults from the command line for special needs.

Environment variables:

MAKEFLAGS: This environment variable, if it exists, is read by the make utility, and is treated as a set of option characters to be used as the default options. Command-line options to make have precedence over these options.
After make has started and the MAKEFLAGS variable has been read, all of the options except -d, -f, and -p are added to the MAKEFLAGS macro. The MAKEFLAGS macro is passed into the environment as an environment variable for all child processes.
SHELL: The value of the SHELL environment variable is always ignored. All other environment variables are used as macros.

Exit status:

When the -q option has been specified:

0: Successful.
1: The target wasn't up-to-date.
>1: An error occurred.

When the -q option hasn't been specified:

0: Successful.
>0: An error occurred.

Contributing author:

GNU

Caveats:

In makefiles, specify Windows pathnames using one of the following methods:

Use a forward slash (/) as a path separator.
Use a backslash (\) escape character before a backslash path separator.
Enclose the entire path in quotation marks.