CLMPCC(4) | Kernel Interfaces Manual (MVME68k) | CLMPCC(4) |
The chip integrates four serial channels in one package, with each channel being completely independent and capable of running in Async (with optional DMA control), Bisync, HDLC/SDLC and X.21 modes. Each channel has 32 bytes of FIFO, split into 16 bytes for the Tx side and 16 bytes for the Rx side.
At the present time, the clmpcc driver supports the non-DMA Async mode of operation, using the channel FIFOs to maximize throughput with minimal interrupt overhead.
The Motorola MVME1x7 boards provide a 20MHz master clock to the device, which allows the Tx and Rx side to be independently set to any baud rate in the range 50 to 57600. The device should be capable of running at a baud rate of 115200, however it is not a rate documented in the device's datasheet for Async. mode so is not recommended.
November 28, 1999 | NetBSD 6.1 |